#ifndef __ASM_ARCH_WS_H
#define __ASM_ARCH_WS_H

#include <linux/init.h>
#include <mach/io.h>

#define SRAM_GRANULARITY		32
#define SRAM_SIZE			(SZ_512K+SZ_128K)


#define RAM_BASE			(0x00100000)
#define DDR_BASE			(0x40000000)
#define GICD_REG_BASE		(GIC_REG_BASE+0x1000)
#define GICC_REG_BASE		(GIC_REG_BASE+0x2000)

#define GIC_REG_BASE			(0x00200000)
#define CPU_SYS_APB_REG_BASE	(0x02E00000)
#define SLV_FW_REG_BASE			(0x02F00000)
#define MEM_FW_REG_BASE			(0x03000000)
#define DMA0_REG_BASE			(0x08000000)
#define DMA1_REG_BASE			(0x08100000)
#define C2C_INTR0_REG_BASE		(0x08200000)
#define C2C_INTR1_REG_BASE		(0x08300000)
#define TOP_SYS_AHB_REG_BASE	(0x10000000)
#define SPINLOCK_REG_BASE		(0x10C00000)
#define RNG_REG_BASE			(0x10D00000)
#define TOP_SYS_APB_REG_BASE	(0x18000000)
#define UART0_REG_BASE			(0x18200000)
#define UART1_REG_BASE			(0x18300000)
#define UART2_REG_BASE			(0x18400000)
#define UART3_REG_BASE			(0x18500000)
#define UART4_REG_BASE			(0x18600000)
#define UART5_REG_BASE			(0x18700000)
#define RSA_REG_BASE			(0x18D00000)
#define HASH_REG_BASE			(0x18E00000)
#define I2C0_REG_BASE			(0x19700000)
#define I2C1_REG_BASE			(0x19800000)
#define I2C2_REG_BASE			(0x19900000)
#define I2C3_REG_BASE			(0x19A00000)
#define I2C4_REG_BASE			(0x19B00000)
#define I2C5_REG_BASE			(0x19C00000)
#define I2S_REG_BASE			(0x19D00000)
#define TOP_PRE_DIV_RF_REG_BASE	(0x19F00000)
#define TOP_CLK_RF_REG_BASE		(0x19F00200)
#define TOP_CLK_GATE_RF_REG_BASE (0x19F00400)
#define TIMER0_REG_BASE			(0x1A000000)
#define TIMER1_REG_BASE			(0x1A100000)
#define TIMER2_REG_BASE			(0x1A200000)
#define SYS_TIMER_REG_BASE		(0x1A700000)
#define RTC_REG_BASE			(0x1A800000)
#define WDT0_REG_BASE			(0x1A900000)
#define WDT1_REG_BASE			(0x1AA00000)
#define GPIO0_REG_BASE			(0x1B000000)
#define GPIO1_REG_BASE			(0x1B010000)
#define GPIO2_REG_BASE			(0x1B020000)
#define GPIO3_REG_BASE			(0x1B030000)
#define GPIO4_REG_BASE			(0x1B040000)
#define SPI0_REG_BASE			(0x1B700000)
#define SPI1_REG_BASE			(0x1B800000)
#define INT_CTRL0_REG_BASE		(0x1BC00000)
#define INT_CTRL1_REG_BASE		(0x1BD00000)
#define INT_CTRL2_REG_BASE		(0x1BE00000)
#define INT_CTRL3_REG_BASE		(0x1BF00000)
#define PWM_REG_BASE			(0x1C000000)
#define SRC_REG_BASE			(0x1C100000)
#define CEN_GLB_APB_REG_BASE	(0x1CD00000)
#define CEN_PIN_REG_BASE		(0x1D100000)
#define HKISP_REG_BASE			(0x20000000)
#define VDU_SYS_PIN_REG_BASE	(0x24000000)
#define VDU_SYS_APB_REG_BASE	(0x24100000)
#define VDU_REG_BASE			(0x24200000)
#define G2D_REG_BASE			(0x24300000)
#define KCF_REG_BASE			(0x24400000)
#define VOU_REG_BASE			(0x24500000)
#define VPPU_REG_BASE			(0x24600000)
#define GMAC0_REG_BASE			(0x24700000)
#define GMAC1_REG_BASE			(0x24800000)
#define SADC_REG_BASE			(0x24900000)
#define ACW_REG_BASE			(0x24A00000)
#define EPHY_REG_BASE			(0x24C00000)
#define DSI_REG_BASE			(0x25C00000)
#define EFUSE_REG_BASE			(0x25D00000)
#define JPEG_REG_BASE			(0x26400000)
#define BGM_REG_BASE			(0x26500000)
#define AES_REG_BASE			(0x26600000)
#define SDIO1_REG_BASE			(0x26700000)
#define CVBS_REG_BASE			(0x26800000)
#define IVE_REG_BASE			(0x26900000)
#define AVE_REG_BASE			(0x26A00000)
#define DMC_SYS_APB_REG_BASE	(0x2C000000)
#define DMC_REG_REG_BASE		(0x2C100000)
#define DDR_PHY_REG_BASE		(0x2C200000)
#define DFI_MON_REG_BASE		(0x2C400000)
#define DDR_FW_REG_BASE			(0x2C500000)
#define PERF_MON0_REG_BASE		(0x2C700000)
#define PERF_MON1_REG_BASE		(0x2C800000)
#define PERF_MON2_REG_BASE		(0x2C900000)
#define PERF_MON3_REG_BASE		(0x2CA00000)
#define PERF_MON4_REG_BASE		(0x2CB00000)
#define PERF_MON5_REG_BASE		(0x2CC00000)
#define NNP_SYS_PIN_REG_BASE	(0x30000000)
#define NNP_SYS_APB_REG_BASE	(0x30100000)
#define EMMC_PHY_REG_BASE		(0x30700000)
#define SFC_REG_BASE			(0x30800000)
#define USB3_PHY_REG_BASE		(0x31000000)
#define EMMC_REG_BASE			(0x32100000)
#define SDIO0_REG_BASE			(0x32200000)
#define USB2_REG_BASE			(0x32300000)
#define USB3_REG_BASE			(0x32400000)
#define ISP_SYS_PIN_REG_BASE	(0x34000000)
#define ISP_SYS_APB_REG_BASE	(0x34100000)
#define VPU_REG_BASE			(0x34C00000)
#define ISP0_REG_BASE			(0x34D00000)
#define ISP1_REG_BASE			(0x34E00000)
#define VEU_SYS_AHB_REG_BASE	(0x38100000)
#define VEU_REG_BASE			(0x38C00000)
#define PTS_REG_BASE			(0x38900000)

/* sys reg io maps */
#define SYS_REG_V2P(va)		((((va)&0xfffff000)<<8)+((va)&0xfff))
#define SYS_REG_P2V_OFF(pa)		(((pa)>>8)+((pa)&0xfff))
#define SYS_REG_P2V(pa)		(VA_SYS_REG_BASE+SYS_REG_P2V_OFF(pa))
#define VA_SYS_REG_BASE		(0xFF000000)

#define VA_CPU_SYS_APB_REG_BASE		(SYS_REG_P2V(CPU_SYS_APB_REG_BASE))
#define VA_TOP_SYS_AHB_REG_BASE		(SYS_REG_P2V(TOP_SYS_AHB_REG_BASE))
#define VA_TOP_SYS_APB_REG_BASE		(SYS_REG_P2V(TOP_SYS_APB_REG_BASE))
#define VA_TOP_PRE_DIV_RF_REG_BASE	(SYS_REG_P2V(TOP_PRE_DIV_RF_REG_BASE))
#define VA_CEN_GLB_APB_REG_BASE		(SYS_REG_P2V(CEN_GLB_APB_REG_BASE))
#define VA_VDU_SYS_APB_REG_BASE		(SYS_REG_P2V(VDU_SYS_APB_REG_BASE))
#define VA_DMC_SYS_APB_REG_BASE		(SYS_REG_P2V(DMC_SYS_APB_REG_BASE))
#define VA_NNP_SYS_APB_REG_BASE		(SYS_REG_P2V(NNP_SYS_APB_REG_BASE))
#define VA_ISP_SYS_APB_REG_BASE		(SYS_REG_P2V(ISP_SYS_APB_REG_BASE))
#define VA_VEU_SYS_AHB_REG_BASE		(SYS_REG_P2V(VEU_SYS_AHB_REG_BASE))
#define VA_PTS_REG_BASE				(SYS_REG_P2V(PTS_REG_BASE))

/* pin reg io maps */
#define VA_CEN_PIN_REG_BASE			(SYS_REG_P2V(CEN_PIN_REG_BASE))
#define VA_VDU_SYS_PIN_REG_BASE		(SYS_REG_P2V(VDU_SYS_PIN_REG_BASE))
#define VA_NNP_SYS_PIN_REG_BASE		(SYS_REG_P2V(NNP_SYS_PIN_REG_BASE))
#define VA_ISP_SYS_PIN_REG_BASE		(SYS_REG_P2V(ISP_SYS_PIN_REG_BASE))

#define VA_TOP_CLK_RF_REG_BASE		(VA_TOP_PRE_DIV_RF_REG_BASE + 0x200)
#define VA_TOP_CLK_GATE_RF_REG_BASE	(VA_TOP_PRE_DIV_RF_REG_BASE + 0x400)

/* CPU_SYS_APB_REG_BASE */
#define REG_CPU_SOFT_RST	(SYS_REG_P2V_OFF(CPU_SYS_APB_REG_BASE) + 0x10)
#define REG_CPU_CORE_CTRL	(SYS_REG_P2V_OFF(CPU_SYS_APB_REG_BASE) + 0x14)
#define REG_CPU_ADDR_MSB_SEL	(SYS_REG_P2V_OFF(CPU_SYS_APB_REG_BASE) + 0x104)
#define REG_DMA_SEL_LOW		(SYS_REG_P2V_OFF(CPU_SYS_APB_REG_BASE) + 0x10C)
#define REG_DMA_SEL_HIGH	(SYS_REG_P2V_OFF(CPU_SYS_APB_REG_BASE) + 0x110)
#define REG_CPU_CORE1_CTRL	(SYS_REG_P2V_OFF(CPU_SYS_APB_REG_BASE) + 0x114)
#define REG_CPU_CORE1_START_ADDR (SYS_REG_P2V_OFF(CPU_SYS_APB_REG_BASE) + 0x118)
#define REG_CPU_CORE2_CTRL	(SYS_REG_P2V_OFF(CPU_SYS_APB_REG_BASE) + 0x11c)
#define REG_CPU_CORE2_START_ADDR (SYS_REG_P2V_OFF(CPU_SYS_APB_REG_BASE) + 0x120)
#define REG_DMA0_AXCACHE	(SYS_REG_P2V_OFF(CPU_SYS_APB_REG_BASE) + 0x1d4)
#define REG_DMA1_AXCACHE	(SYS_REG_P2V_OFF(CPU_SYS_APB_REG_BASE) + 0x1d8)

/* VDU_SYS_APB_REG_BASE */
#define REG_EFUSE_CTRL_16	(SYS_REG_P2V_OFF(VDU_SYS_APB_REG_BASE) + 0x1c0)

#define CPU1_RST_BIT			1
#define CPU2_RST_BIT			10

/* TOP_SYS_APB_REG_BASE */
#define REG_CEN_PERI_CLK_CTRL      (SYS_REG_P2V_OFF(TOP_SYS_APB_REG_BASE) + 0x0)
#define REG_CEN_PERI_APB_CLK_CTRL  (SYS_REG_P2V_OFF(TOP_SYS_APB_REG_BASE) + 0x4)
#define REG_CEN_PERI_APB_CLK_CTRL1 (SYS_REG_P2V_OFF(TOP_SYS_APB_REG_BASE) + 0x8)
#define REG_SPI0_MODE             (SYS_REG_P2V_OFF(TOP_SYS_APB_REG_BASE) + 0x30)
#define REG_AP_PERI_SOFT_RST0      (SYS_REG_P2V_OFF(TOP_SYS_APB_REG_BASE) + 0xc)
#define HASH_SOFT_RST		28
#define RSA_SOFT_RST		27
#define RNG_SOFT_RST		26
#define PWM_SOFT_RST		25
#define SPI0_SOFT_RST		24
#define SFC_SOFT_RST		23
#define SRC_SOFT_RST		22
#define RTCT_SOFT_RST		21
#define GPIO_SOFT_RST		20
#define I2S0_SOFT_RST		19
#define I2C5_SOFT_RST		18
#define I2C4_SOFT_RST		17
#define I2C3_SOFT_RST		16
#define I2C2_SOFT_RST		15
#define I2C1_SOFT_RST		14
#define I2C0_SOFT_RST		13
#define UART5_SOFT_RST		12
#define UART4_SOFT_RST		11
#define UART3_SOFT_RST		10
#define UART2_SOFT_RST		9
#define UART1_SOFT_RST		8
#define UART0_SOFT_RST		7
#define IR_SOFT_RST			6
#define TIMER2_SOFT_RST		5
#define TIMER1_SOFT_RST		4
#define TIMER0_SOFT_RST		3
#define WDT1_SOFT_RST		2
#define WDT0_SOFT_RST		1
#define SYST_SOFT_RST		0

#define REG_IIS0_CLK_CTRL	(SYS_REG_P2V_OFF(TOP_SYS_APB_REG_BASE) + 0x10)
#define CKG_I2S_FRAC_DIV_EN		BIT(4)
#define CKG_I2S_FAST_EN			BIT(3)
#define CKG_I2S_SOURCE_SEL		BIT(2)
#define CKG_I2S_REV				BIT(1)
#define I2S_MCLK_SEL			BIT(0)
#define REG_CKG_I2S_FRAC_DIV_M	(SYS_REG_P2V_OFF(TOP_SYS_APB_REG_BASE) + 0x14)
#define REG_CKG_I2S_FRAC_DIV_N	(SYS_REG_P2V_OFF(TOP_SYS_APB_REG_BASE) + 0x18)
#define REG_CKG_I2S0_CTL	(SYS_REG_P2V_OFF(TOP_SYS_APB_REG_BASE) + 0x28)

/* CEN_GLB_APB_REG_BASE */
#define REG_GLB_RESET		(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0xac)
#define SW_GLB_RST				(BIT(0))
#define SW_EXT_RST				(BIT(1))

#define REG_WR_PROTECT		(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0xb0)
#define REG_PMU_CHIP_ID		(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x300)
#define REG_PMU_BOOT_MODE	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x308)
#define REG_PMU_DDR_SIZE	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x30c)
#define REG_PMU_RESERVED2	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x310)
#define REG_PMU_CHIP_INFO	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x314)
#define REG_PMU_EPHY_PARAM	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x318)
#define REG_PMU_RTC_PARAM	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x31c)
#define REG_PMU_UPLL_CTRL0	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0xd4)
#define REG_PMU_UPLL_CTRL1	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0xd8)
#define REG_PMU_EPLL_CTRL0	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0xe0)
#define REG_PMU_EPLL_CTRL1	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0xe4)
#define REG_PMU_VPLL_CTRL0	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0xec)
#define REG_PMU_VPLL_CTRL1	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0xf0)
#define REG_PMU_MPLL_CTRL0	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0xf8)
#define REG_PMU_MPLL_CTRL1	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0xfc)
#define REG_PMU_CPLL_CTRL0	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x110)
#define REG_PMU_CPLL_CTRL1	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x114)
#define REG_PMU_DPLL_CTRL0	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x120)
#define REG_PMU_DPLL_CTRL1	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x124)



/* DMC_SYS_APB_REG_BASE */
#define REG_DFIMON_TMR1_CTRL0	(SYS_REG_P2V_OFF(DMC_SYS_APB_REG_BASE) + 0x0)
#define REG_DFIMON_TMR1_CTRL1	(SYS_REG_P2V_OFF(DMC_SYS_APB_REG_BASE) + 0x4)
#define REG_DFIMON_TMR1_CTRL2	(SYS_REG_P2V_OFF(DMC_SYS_APB_REG_BASE) + 0x8)
#define REG_HIGH_LEN_TIMER1	(REG_DFIMON_TMR1_CTRL1)
#define REG_LOW_LEN_TIMER1	(REG_DFIMON_TMR1_CTRL2)
#define REG_DMC_CLK_CTRL	(SYS_REG_P2V_OFF(DMC_SYS_APB_REG_BASE) + 0x300)
#define REG_PERF_TRIGGER	(SYS_REG_P2V_OFF(DMC_SYS_APB_REG_BASE) + 0xB04)

/* NNP_SYS_APB_REG_BASE */
#define REG_EMMC_CLK_RST_CTRL0	(SYS_REG_P2V_OFF(NNP_SYS_APB_REG_BASE) + 0x200)
#define REG_EMMC_CLK_RST_CTRL1	(SYS_REG_P2V_OFF(NNP_SYS_APB_REG_BASE) + 0x204)
#define EMMC_HOST_SOFT_RST		(1)
#define EMMC_PHY_SOFT_RST		(0)
#define REG_EMMC_CARD_PAD_SEL	(SYS_REG_P2V_OFF(NNP_SYS_APB_REG_BASE) + 0x208)
#define REG_USB2_CLK_RST_CTRL	(SYS_REG_P2V_OFF(NNP_SYS_APB_REG_BASE) + 0x300)
#define REG_USB3_CLK_RST_CTRL	(SYS_REG_P2V_OFF(NNP_SYS_APB_REG_BASE) + 0x400)
#define REG_SDIO0_CLK_RST_CTRL	(SYS_REG_P2V_OFF(NNP_SYS_APB_REG_BASE) + 0x500)

/* VEU_SYS_AHB_REG_BASE */
#define REG_PTS_CTRL0		(SYS_REG_P2V_OFF(VEU_SYS_AHB_REG_BASE) + 0x40)
#define REG_PTS_CTRL1		(SYS_REG_P2V_OFF(VEU_SYS_AHB_REG_BASE) + 0x44)
#define REG_PTS_CTRL2		(SYS_REG_P2V_OFF(VEU_SYS_AHB_REG_BASE) + 0x48)

#define REG_PTS_UPDATE		(SYS_REG_P2V_OFF(PTS_REG_BASE) + 0x0)

#define CONSOLE_REG_BASE		UART0_REG_BASE
#define FH_UART_NUMBER			6

#define SDIO0_CLK_RST_CTRL		(VA_NNP_SYS_APB_REG_BASE + 0x500)

#define	AXI_SDIO0_EN			BIT(5)
#define	SDIO0_CLK_SEL			(0x3 << 3)
#define	SDIO0_SOFT_RST			BIT(2)
#define	SDIO0_DLLREF_EN			BIT(1)
#define	SDIO0_EN				BIT(0)

#define SDIO0_CTRL0			(VA_NNP_SYS_APB_REG_BASE + 0x504)
#define SDIO0_CTRL1			(VA_NNP_SYS_APB_REG_BASE + 0x508)
#define SDIO0_DLLINCTRLREG_SPL	(VA_NNP_SYS_APB_REG_BASE + 0x50c)
#define SDIO0_DLLININFOREG_SPL	(VA_NNP_SYS_APB_REG_BASE + 0x510)
#define SDIO0_DLLOUTREG_SPL		(VA_NNP_SYS_APB_REG_BASE + 0x514)
#define SDIO0_DLLINCTRLREG_DRV	(VA_NNP_SYS_APB_REG_BASE + 0x518)
#define SDIO0_DLLININFOREG_DRV	(VA_NNP_SYS_APB_REG_BASE + 0x51c)
#define SDIO0_DLLOUTREG_DRV		(VA_NNP_SYS_APB_REG_BASE + 0x520)

#define CK_CTRL0				(VA_VDU_SYS_APB_REG_BASE + 0x0)
#define	SDIO1_CLK_SEL			(0x3 << 18)
#define	SDIO1_DLLREF_EN			BIT(21)
#define	SDIO1_EN				BIT(20)

#define CK_CTRL2				(VA_VDU_SYS_APB_REG_BASE + 0x8)
#define	AXI_SDIO1_EN			BIT(10)

#define SOFT_RST0				(VA_VDU_SYS_APB_REG_BASE + 0x64)
#define	SDIO1_SOFT_RST			BIT(18)

#define SDIO1_CTRL0	(VA_VDU_SYS_APB_REG_BASE + 0x124)
#define SDIO1_DLLINCTRLREG_SPL	(VA_VDU_SYS_APB_REG_BASE + 0x128)
#define SDIO1_DLLININFOREG_SPL	(VA_VDU_SYS_APB_REG_BASE + 0x12c)
#define SDIO1_DLLOUTREG_SPL		(VA_VDU_SYS_APB_REG_BASE + 0x130)
#define SDIO1_DLLINCTRLREG_DRV	(VA_VDU_SYS_APB_REG_BASE + 0x134)
#define SDIO1_DLLININFOREG_DRV	(VA_VDU_SYS_APB_REG_BASE + 0x138)
#define SDIO1_DLLOUTREG_DRV		(VA_VDU_SYS_APB_REG_BASE + 0x13c)
#define SDIO1_CTRL1	(VA_VDU_SYS_APB_REG_BASE + 0x148)


#define TMR0_IRQ			32
#define TMR1_IRQ			33
#define TMR2_IRQ			34
#define SYS_TIMER_IRQ		35
#define WDT0_IRQ			36
#define RTC_IRQ				37
#define RTC_CORE_ALARM_IRQ	38
#define SFC_IRQ			39
#define SPI0_IRQ			40
#define SPI1_IRQ			41
#define PWM_IRQ				42
#define AES_IRQ				43
#define UART0_IRQ			44
#define UART1_IRQ			45
#define UART2_IRQ			46
#define UART3_IRQ			47
#define UART4_IRQ			48
#define UART5_IRQ			49
#define I2C0_IRQ			50
#define I2C1_IRQ			51
#define I2C2_IRQ			52
#define I2C3_IRQ			53
#define I2C4_IRQ			54
#define I2C5_IRQ			55
#define I2S0_IRQ			56
#define DMA0_IRQ			57
#define DMA1_IRQ			58
#define DSI_IRQ				59
#define SDIO0_IRQ			60
#define SDIO1_IRQ			61
#define RSA_IRQ				62
#define HASH_IRQ			63
#define RNG_IRQ				64
#define GPIO0_IRQ			65
#define GPIO1_IRQ			66
#define GPIO2_IRQ			67
#define GPIO3_IRQ			68
#define LPDDR_TEMP_IRQ		69
#define DDR_FW_IRQ			70
#define MEM_FW_IRQ			73
#define SLV_FW_IRQ			74
#define GPIO4_IRQ			76
#define WDT1_IRQ			78
#define GMAC0_SBD_INTR_IRQ		83
#define GMAC0_SBD_PERCH_TX0_IRQ	84
#define GMAC0_SBD_PERCH_TX1_IRQ	85
#define GMAC0_SBD_PERCH_RX0_IRQ	86
#define GMAC0_SBD_PERCH_RX1_IRQ	87
#define GMAC1_SBD_INTR_IRQ		88
#define GMAC1_SBD_PERCH_TX0_IRQ	89
#define GMAC1_SBD_PERCH_TX1_IRQ	90
#define GMAC1_SBD_PERCH_RX0_IRQ	91
#define GMAC1_SBD_PERCH_RX1_IRQ	92
#define USB2_IRQ			93
#define USB3_IRQ			94
#define KCF0_IRQ			95
#define KCF1_IRQ			96
#define KCF2_IRQ			97
#define KCF_BUFM_IRQ		98
#define VDAC_CVBS_IRQ		99
#define VOU_DHD_IRQ			100
#define VOU_DSD_IRQ			101
#define VEU_A_IRQ			102
#define VEU_B_IRQ			103
#define VEU_C_IRQ			104
#define VEU_D_IRQ			105
#define VEU_SYS_PERF_MON_IRQ	106
#define EMMC_IRQ			107
#define EMMC_PHY_IRQ		108
#define EMMC_WAKEUP_IRQ		109
#define G2D_IRQ				110
#define JPG_IRQ				111
#define VPPU0_IRQ			112
#define BGM_IRQ				113
#define IVE_IRQ				114
#define VPPU1_IRQ			115
#define VDEC_IRQ			116
#define SADC_IRQ			117
#define ACODEC_IRQ			118
#define HKISP_IRQ			121
#define AVE_IRQ				122
#define VDU_SYS_PERF_MON_IRQ	123
#define VPU_IRQ				124
#define ISP0_IRQ			125
#define ISP1_IRQ			126
#define VICAP_IRQ			127
#define ISP_SYS_PERF_MON_IRQ	128
#define NNP0_IRQ			129
#define NNP1_IRQ			130
#define NNP2_IRQ			131
#define CR0_IRQ				132
#define CR1_IRQ				133
#define CR2_IRQ				134
#define BUFM_IRQ			135
#define NNP_SYS_PERF_MON_IRQ	136
#define CPU_SYS_PERF_MON_IRQ	137
#define DMC_PRIO_CTRL_IRQ	138
#define DFI_ALERT_ERR_IRQ	139
#define DFI_MON_IRQ			140
#define DMC_PORT_MPU_IRQ	141
#define DMC_PERF_MON_IRQ	142
#define DMC_PORT_POISON_IRQ	143
#define MCU_CA7_IRQ0_IRQ	146
#define MCU_CA7_IRQ1_IRQ	147
#define MCU_CA7_IRQ2_IRQ	148
#define MCU_CA7_IRQ3_IRQ	149
#define MCU_CA7_IRQ4_IRQ	150
#define MCU_CA7_IRQ5_IRQ	151
#define MCU_CA7_IRQ6_IRQ	152
#define MCU_CA7_IRQ7_IRQ	153
#define MCU_CA7_COMBIRQ_IRQ	154
#define A7_NAXIERRIRQ_IRQ	155
#define NCTIIRQ_IRQ			156
#define A7_COMMTX_IRQ		157
#define A7_COMMRX_IRQ		158
#define A7_PMUIRQ_IRQ		159

#define MEM_START_PHY_ADDR	DDR_BASE
#define MEM_SIZE			0x10000000

/* FH Serial HardWare HandShake */
#define UART1_TX_HW_HANDSHAKE   (9)
#define UART1_RX_HW_HANDSHAKE   (8)
#define UART2_TX_HW_HANDSHAKE   (15)
#define UART2_RX_HW_HANDSHAKE   (14)
#define UART3_TX_HW_HANDSHAKE   (13)
#define UART3_RX_HW_HANDSHAKE   (12)
#define UART1_DMA_TX_CHAN       (2)
#define UART1_DMA_RX_CHAN       (3)
#define UART2_DMA_TX_CHAN       (4)
#define UART2_DMA_RX_CHAN       (5)
#define UART3_DMA_TX_CHAN       (6)
#define UART3_DMA_RX_CHAN       (7)

/* timer clk  fpga 1M,soc 50M*/
#define TIMER_CLK			(1000000)

/*sdio*/
#define SIMPLE_0     (0)
#define SIMPLE_90    (4)
#define SIMPLE_180   (8)
#define SIMPLE_270   (12)


#define SDIO0_RST_BIT       (~UL(1<<2))
#define SDIO0_CLK_RATE      (50000000)
#define SDIO0_CLK_DRV_SHIFT (20)
#define SDIO0_CLK_DRV_DEGREE (SIMPLE_180)
#define SDIO0_CLK_SAM_SHIFT (16)
#define SDIO0_CLK_SAM_DEGREE (SIMPLE_0)


#define SDIO1_RST_BIT       (~UL(1<<1))
#define SDIO1_CLK_RATE      (50000000)
#define SDIO1_CLK_DRV_SHIFT (12)
#define SDIO1_CLK_DRV_DEGREE (SIMPLE_180)
#define SDIO1_CLK_SAM_SHIFT (8)
#define SDIO1_CLK_SAM_DEGREE (SIMPLE_0)

#define SDC0_HRSTN  (0x1<<2)
#define SDC1_HRSTN  (0x1<<1)
#define SDC2_HRSTN  (0)


/*usb*/
#define IRQ_UHOST          USBC_IRQ
#define FH_PA_OTG          USBC_REG_BASE
#define IRQ_OTG            IRQ_UHOST
#define FH_SZ_USBHOST	   SZ_1M
#define FH_SZ_OTG          SZ_1M

#define USB_UTMI_RST_BIT      (0x1<<1)
#define USB_PHY_RST_BIT       (0x11)
#define USB_SLEEP_MODE_BIT    (0x1<<24)
#define USB_IDDQ_PWR_BIT    (0x1<<10)


#define CLK_SCAN_BIT_POS                (28)
#define INSIDE_PHY_ENABLE_BIT_POS       (24)
#define MAC_REF_CLK_DIV_MASK            (0x0f)
#define MAC_REF_CLK_DIV_BIT_POS         (24)
#define MAC_PAD_RMII_CLK_MASK           (0x0f)
#define MAC_PAD_RMII_CLK_BIT_POS        (24)
#define MAC_PAD_MAC_REF_CLK_BIT_POS     (28)
#define ETH_REF_CLK_OUT_GATE_BIT_POS    (25)
#define ETH_RMII_CLK_OUT_GATE_BIT_POS   (28)
#define IN_OR_OUT_PHY_SEL_BIT_POS       (26)
#define INSIDE_CLK_GATE_BIT_POS         (0)
#define INSIDE_PHY_SHUTDOWN_BIT_POS     (31)
#define INSIDE_PHY_RST_BIT_POS          (30)
#define INSIDE_PHY_TRAINING_BIT_POS     (27)
#define INSIDE_PHY_TRAINING_MASK        (0x0f)

#define TRAINING_EFUSE_ACTIVE_BIT_POS          4

#define I2S_CLK_FREQ		648000000 /* 648M */

#endif /* __ASM_ARCH_WS_H */
